MAP electronics Cocerto-B Especificações descarregar pdf (Página 10)

Known Design Marginality/Exceptions to Functional Specifications

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Advisory Control Subsystem: Reset Value (/8) of CCLKCTL.CLKDIV Bit Field Violates the

MIN Requirement Mandated by the Data Manual for ACIBCLK, When the Input

Clock to the Divider is Less Than 40 MHz

Revision(s) Affected 0

Details On power up or after an external reset (XRS), PLL is bypassed and the Master Boot

ROM configures the default SYSCLK divider to "/1". This makes the input clock to the

divider the same as OSCCLK. If OSCCLK is less than 40 MHz, then upon power up or

an external reset, ACIBCLK would be less than 5 MHz. However, this is not an issue

because the Analog Subsystem needs not be functional during boot time.

Workaround(s) An OTP function is provided in the Control Subsystem for users to call during their

application initialization process and before using Analog Subsystem peripherals on the

device. This function will configure the CCLKCTL divider as needed by the application.

This will be fixed in the next revision of the silicon.

F28M35x Concerto MCU Silicon Errata SPRZ357B– August 2011– Revised January 2012

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MAP electronics Cocerto-B Especificações Página 10