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Usage Notes and Known Design Exceptions to Functional Specifications
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Table 5. List of Advisories (continued)
SILICON REVISION(S)
AFFECTED
TITLE
0 A B
Master Subsystem I
2
C: Data Hold Time Violates Philips® I
2
C Specification Yes
Master Subsystem MPU: Memory Protection Unit is Disabled Yes
Master Subsystem Boot ROM: NMI Handler Can Return Before Clearing All the Pending NMIs, Yes
if There is a Nested NMI
Master Boot ROM: NMI Handler Not Executed if NMI Occurs at Power Up or Immediately After Yes
a Reset
Master Boot ROM: Parallel Boot Mode Will Not Work as Intended Yes
C28x Flash: Code Executing From the C28x Subsystem Flash May be Subject to Unnecessary Yes
1-Cycle Delays
C28x Flash: The SBF and BF Instructions Will Not Execute From Flash Yes
C28x Clocking: EALLOW Protection of C28x Clocking Registers Prevents Read of Registers Yes
μDMA: No Transfer Completion Interrupt From SW Channels, Other Than Channel 30 Yes
VCU: First CRC Calculation May Not be Correct Yes
Flash ECC: When Program/Data Cache is Enabled, ECC Errors are Captured Only on a Single Yes
64-Bit Slice and Not on the Full 128-Bit Flash Bank Data Width
Flash ECC: C28x 'Flash Uncorrectable' Error Generated When Executing F021 Flash API Yes
Functions With Flash ECC Enabled
Temperature Sensor: getTempSlope() and getTempOffset() Functions are not Available on Yes
TMX Silicon
EMAC: Resetting EMAC Controller Using SRCR2 Register Does Not Automatically Reset the Yes
Ethernet PHY Via MII_PHYRST Signal
Read of Clock Control Registers on C28x Memory Map is EALLOW-Protected Yes
CPU Self Test (HWBIST) is not Supported on Revision 0 Devices Yes
EPI: C28x Access to the EPI Bus on the Device Yes
PBIST: DCAN0 Memory Cannot be Tested in Stand-alone Configuration Yes
12
F28M35x Concerto™ MCU Silicon Errata SPRZ357JAugust 2011Revised July 2014
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