www.ti.com
Usage Notes and Known Design Exceptions to Functional Specifications
4.1.2 EPI: New Feature Addition to EPI Module Usage Note
Revision(s) Affected: A, B
In the EPI module, many new features have been added on silicon revisions A and onwards. New
configuration registers have been added to enable new features. However, in some cases, new
configuration bits (which were “Reserved” on the revision 0 silicon) have been added to existing registers,
without breaking the compatibility with the revision 0 silicon. Users should refer to the "External Peripheral
Interface (EPI)" chapter in the Concerto F28M35x Technical Reference Manual (SPRUH22) to make sure
their existing EPI code (which works on the revision 0 silicon) is not changing the default value of the new
configuration bits. Otherwise, the old code may not work on the new silicon.
4.1.3 EPI: ALE Signal Polarity Usage Note
Revision(s) Affected: A, B
On the revision 0 silicon, the polarity of the ALE (address latch enable) signal was active HIGH and it was
not configurable. On new silicon revisions, a configuration bit (ALEHIGH) has been added in existing host
bus configuration registers so that the user can configure the polarity of the ALE signal as per system
requirement. Reset value of this bit is set to “1” to have the default polarity of ALE as active HIGH so that
it is compatible with the revision 0 silicon (‘0’ will make it active LOW). Since this configuration field was
reserved in the revision 0 silicon, if the application writes ‘0’ to this field (while configuring other bit fields in
this register), there would be no issue for the revision 0 silicon, but the same code will not work on the
revision A silicon. This is because ‘0’ means active LOW polarity for ALE on revision A silicon. This bit
needs to be set to ‘1’ to make it work on the revision A silicon.
4.1.4 EPI: CS0/CS1 Swap Usage Note
Revision(s) Affected: A, B
On revision A silicon onwards, if the following conditions are true:
• both EPADR and ERADR are not 0x0
• the ECADR field is 0x0
• the EPI is configured for dual-chip selects
then,
• CS0 is asserted for either address range defined by ERADR
• CS1 is asserted for either address range defined by EPADR
This has been changed from revision 0 silicon, where, in the same configuration,
• CS0 is asserted for either address range defined by EPADR
• CS1 is asserted for either address range defined by ERADR.
Table 3. CS0/CS1 Swap
SILICON CHIP SELECT
ERADR EPADR ECADR CS0 CS1
REVISION MODE
EPADR defined ERADR defined
address range address range
0 Dual-chip select 0x1 or 0x2 0x1 or 0x2 0x0
(0xA000.0000 or (0x6000.0000 or
0xC000.0000) 0x8000.0000)
ERADR defined EPADR defined
address range address range
A and onwards Dual-chip select 0x1 or 0x2 0x1 or 0x2 0x0
(0x6000.0000 or (0xA000.0000 or
0x8000.0000) 0xC000.0000)
7
SPRZ357J–August 2011–Revised July 2014 F28M35x Concerto™ MCU Silicon Errata
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
(20 páginas)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais